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BiCS-Feature

Western Digital and Toshiba have jointly announced that they have begun initial production on 64-layer 3D NAND in 512Gb capacities. This new airplane pilot product at the company's fab in Yokkaichi, Japan, is expected to ramp up to commercial volumes within the first half of 2017, with hardware arriving on shop shelves not as well long thereafter.

"The launch of the industry's first 512Gb 64-layer 3D NAND chip is some other of import stride forward in the advocacy of our 3D NAND engineering science, doubling the density from when we introduced the world's first 64-layer architecture in July 2016," said Dr. Siva Sivaram, executive vice president, retentivity technology, Western Digital. "This is a great addition to our rapidly broadening 3D NAND technology portfolio. Information technology positions u.s.a. well to continue addressing the increasing demand for storage due to rapid data growth across a wide range of customer retail, mobile and information center applications."

Whether Samsung or Toshiba/WD are "beginning" to 64-layer NAND depends on whether you care to measure in technology press releases or aircraft products. Neither company has, as of yet, really shipped 64-layer NAND. Toshiba and Western Digital utilize what they refer to as Bit Price Scaling (BiCS) technology, though the actual variations between this approach and the V-NAND manufactured by Samsung are unclear. Both Samsung and WD/Toshiba utilise charge-trap flash as opposed to a floating-gate — Micron is the only 3D NAND manufacturer using a floating-gate construction at this point in time.

BiCS3

The only other clue virtually BiCS is that it uses unlike materials in cell construction. Samsung's V-NAND is built on SONOS — Silicon-Oxide-Nitride-Oxygen-Silicon, equally opposed to using polysilicon. TANOS uses TaN, AL2O3, SiiiiNfour, SiO2, and Si — which is probably why we call information technology TANOS in the first place. The benefits of this construction method take not been well explained; all of the firms working on 3D NAND have been repose about what the specific benefits are of their particular approaches and technologies and take generally described them in only very general terms.

Reaching full commercialization of BiCS would be a significant step for Western Digital. The starting time BiCS, which Toshiba announced back in 2015, was a 48-layer pilot production production that never made it into shipping products. BiCS2 has supposedly been shipped to OEMs and customers, though I'm non enlightened of any SSDs that employ it (this doesn't mean nobody uses information technology; but low-cost OEMs or parts sold for system integration might not advertise the fact).

It'll besides be interesting to see how the reliability and performance metrics shape up for these new triple-layer prison cell products. Manufacturers like Samsung and WD are trying to get away from TLC, probably because the NAND blazon is known to have much lower performance and reliability compared with MLC. It'll be interesting to encounter how many of these characteristics carry over to 3D NAND. Samsung uses its 40nm procedure for all of its current 3D NAND products, at least as far as we know, which means these 40nm TLC drives accept, in some cases, reliability metrics that compare well against 20nm planar MLC NAND.

For now, we're sticking with the TLC acronym to discuss both 2D and 3D NAND, since the term refers to the amount of information stored within each NAND prison cell, non whatever associated metrics related to reliability. Western Digital's new 512Gb capacities also put it on par with Samsung, which appear similar capacities for its upcoming 64-layer 3D NAND, which is also expected to transport in 2017.

At present read: How do SSDs piece of work?